1. Field of the Invention
The present invention relates in general to the field of information handling system power control, and more particularly to a method and system for feed forward control loop optimization of processor power.
2. Description of the Related Art
As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
One reason that information handling systems have grown in capability over time is that the microprocessors that run as central processing units (CPUs) for information handling systems have packed an increasing number of circuits in a given space. Microprocessors with greater numbers of circuits have greater processing power to perform information processing but also have greater power demands and greater variations in power demand over time. For instance, present state-of-the-art microprocessors have relatively large load steps, such as 80 amps at rates of 400 amps per microsecond, which require power supplies to have relatively low output impedance. Future microprocessors will likely have even greater step loads and higher slew rates as microprocessor circuit density continues to increase. Further, as microprocessors grow more complex, the tolerances for power supply processor voltage requirements will narrow so that power supplies must respond to changes in microprocessor power use even more rapidly and with greater accuracy, which will result in increasingly expensive power supply solutions.
One solution for control of power supplied to a microprocessor is to use feedback of voltage and current provided by the power supply with conventional loop optimization techniques and sufficient output capacitance to meet the microprocessor current and voltage requirements. One difficulty with this solution is that, as the current slew rates expected of the power supply increase and the tolerances of the microprocessor tighten, the number and/or size of output capacitance increases to keep processor voltage within desired tolerances. The capacitors are added at the output of the power supply and the microprocessor to supply current rapidly enough to maintain voltage at the microprocessor within the desired tolerances. However, the addition of capacitance to meet slew rate and tolerance requirements generally increases the size and expense of the power supply. Increased processor current slew rates and narrowing voltage tolerance requirements of present and future microprocessors will result in expensive and large capacitance-based solutions to ensure proper operation of information handling systems.